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isplsi 5384v in-system programmable 3.3v superwide high density pld 1 5384v_09 copyright ?1999 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. july 1999 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com features superwide high density in-system programmable logic 3.3v power supply user selectable 3.3v/2.5v i/o 18,000 pld gates / 384 macrocells up to 288 i/o pins 384 registers high-speed global interconnect superwide 32 generic logic block (glb) size for optimum performance superwide input gating (68 inputs) for fast counters, state machines, address decoders, etc. pcb efficient ball grid array (bga) package options high performance e 2 cmos technology f max = 125 mhz maximum operating frequency t pd = 7.5 ns propagation delay ttl/3.3v/2.5v compatible input thresholds and output levels electrically erasable and reprogrammable non-volatile programmable speed/power logic path optimization in-system programmable ?increased manufacturing yields, reduced time-to- market, and improved product quality ?reprogram soldered devices for faster debugging 100% ieee 1149.1 boundary scan testable and 3.3v in-system programmable architecture features enhanced pin-locking architecture with single- level global routing pool and superwide glbs wrap around product term sharing array supports up to 35 product terms per macrocell macrocells support concurrent combinatorial and registered functions macrocell registers feature multiple control options including set, reset and clock enable four dedicated clock input pins plus macrocell product term clocks slew and skew programmable i/o (saspi/o) supports programmable bus hold, pull-up, open drain and slew and skew rate options six global output enable terms, two global oe pins and one product term oe per macrocell ispdesignexpert ?logic compiler and complete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms functional block diagram global routing pool (grp) boundary scan interface input bus generic logic block input bus generic logic block input bus input bus input bus input bus generic logic block generic logic block generic logic block generic logic block input bus generic logic block input bus generic logic block input bus input bus input bus input bus generic logic block generic logic block generic logic block generic logic block isplsi 5000v description the isplsi 5000v family of in-system programmable high density logic devices is based on generic logic blocks (glbs) of 32 registered macrocells and a single global routing pool (grp) structure interconnecting the glbs. outputs from the glbs drive the global routing pool (grp) between the glbs. switching resources are pro- vided to allow signals in the global routing pool to drive any or all the glbs in the device. this mechanism allows fast, efficient connections across the entire device. each glb contains 32 macrocells and a fully populated, programmable and-array with 160 logic product terms and 5 extra control product terms. the glb has 68 inputs from the global routing pool which are available in both true and complement form for every product term. the 160 product terms are grouped in 32 sets of five and sent into a product term sharing array (ptsa) which allows sharing up to a maximum of 35 product terms for a single function. alternatively, the ptsa can be bypassed for functions of five product terms or less. the five extra product terms are used for shared glb controls, set, reset, clock, clock enable and output enable.
specifications isplsi 5384v 2 global routing pool (grp) boundary scan interface goe0 goe1 set/reset 1. clk2, clk3 and toe signals are multiplexed with i/o signals. which i/o is multiplexed is determined by the package type used ?see table below. tdi tck tms tdo clk 1 clk 0 1 clk 3 1 clk 2 vccio input bus generic logic block input bus generic logic block input bus input bus input bus input bus generic logic block generic logic block generic logic block generic logic block input bus generic logic block input bus generic logic block input bus input bus input bus input bus generic logic block generic logic block generic logic block generic logic block package type multplexed signals 208 pqfp i/o 89 / clk2 i/o 98 / clk3 i/o 0 / toe 208 bga i/o 89 / clk2 i/o 98 / clk3 i/o 0 / toe 272 bga i/o 119 / clk2 i/o 131 / clk3 i/o 0 / toe 388 bga i/o 179 / clk2 i/o 197 / clk3 i/o 0 / toe i/o 167 i/o 166 i/o 165 i/o 164 i/o 147 i/o 146 i/o 145 i/o 144 i/o 191 i/o 190 i/o 189 i/o 188 i/o 171 i/o 170 i/o 169 i/o 168 i/o 215 i/o 214 i/o 213 i/o 212 i/o 195 i/o 194 i/o 193 i/o 192 i/o 72 i/o 73 i/o 74 i/o 75 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 i/o 98 i/o 99 i/o 116 i/o 117 i/o 118 i/o 119 i/o 120 i/o 121 i/o 122 i/o 123 i/o 140 i/o 141 i/o 142 i/o 143 i/o 239 i/o 238 i/o 237 i/o 236 i/o 219 i/o 218 i/o 217 i/o 216 i/o 263 i/o 262 i/o 261 i/o 260 i/o 243 i/o 242 i/o 241 i/o 240 i/o 287 i/o 286 i/o 285 i/o 284 i/o 267 i/o 266 i/o 265 i/o 264 1 i/o 0 / toe i/o 1 i/o 2 i/o 3 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 68 i/o 69 i/o 70 i/o 71 functional block diagram figure 1. isplsi 5384v functional block diagram (388 bga option)
specifications isplsi 5384v 3 isplsi 5000v description (continued) the 32 registered macrocells in the glb are driven by the 32 outputs from the ptsa or the ptsa bypass. each macrocell contains a programmable xor gate, a pro- grammable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. the macrocells each have two outputs, which can be fed back through the global routing pool. this dual output capability from the macrocell allows efficient use of the hardware resources. one output can be a registered function for example, while the other output can be an unrelated combinatorial function. a direct register input from the i/o pad facili- tates efficient use of this feature to construct high-speed input registers. macrocell registers can be clocked from one of several global or product term clocks available on the device. a global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. reset and preset for the macrocell register is provided from both global and product term signals. the macrocell register can be programmed to operate as a d- type register, a d-type latch or a t-type flip flop. the 32 outputs from the glb can drive both the global routing pool and the device i/o cells. the global routing pool contains one line from each macrocell output and one line from each i/o pin. the input buffer threshold has programmable ttl/3.3v/ 2.5v compatible levels. the output driver can source 4ma and sink 8ma. the output drivers have a separate vccio reference input which is independent of the main vcc supply for the device. this feature allows the output drivers to drive either 3.3v or 2.5v output levels while the device logic and the output current drive is always pow- ered from 3.3v. the output drivers also provide individually programmable edge rates and open drain capability. a programmable pullup resistor is provided to tie off un- used inputs and a programmable bus-hold latch is avail- able to hold tristate outputs in their last valid state until the bus is driven again by some device. the isplsi 5000v family features 3.3v, non-volatile in- system programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. programming is achieved through the industry standard ieee 1149.1-compliant boundary scan interface. boundary scan test is also supported through the same interface. an enhanced, multiple cell security scheme is provided that prevents reading of the jedec programming file when secured. after the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. isplsi 5000v family members the isplsi 5000v family ranges from 256 macrocells to 512 macrocells and operates from a 3.3v power supply. all family members will be available with multiple pack- age options. the isplsi 5000v family device matrix showing the various bondout options is shown in the table below. the interconnect structure (grp) is very similar to lattice's existing 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. the isplsi 5000v family does not, however, use registered i/o cells or an output routing pool. table 1. isplsi 5000v family e p y t e g a k c a p e c i v e ds b l gs l l e c o r c a m* a g b 8 0 2p f q p 8 0 2a g b 2 7 2a g b 8 8 3 v 6 5 2 5 i s l p s i 86 5 2o / i 4 4 1o / i 4 4 1o / i 2 9 1 v 4 8 3 5 i s l p s i 2 14 8 3o / i 4 4 1o / i 4 4 1o / i 2 9 1o / i 8 8 2 v 2 1 5 5 i s l p s i 6 12 1 5 o / i 8 8 2 a g b h c t i p e n i f h c t i p l l a b m m 0 . 1 *
specifications isplsi 5384v 4 figure 2. isplsi 5384v block diagram (288 i/o version) 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 5384_288 6/10/97 24 24 24 24 24 24 24 24 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 24 24 32 24 i/o 160 160 pt 160 32 d q 32 24 i/o 68 dq 160 160 68 160 pt 32 32 32 24 24 672 24 24 32 32 24 24 32 32 24 24 32 32 24 24 32 32 24 24 32 32 24 24 5 5 pt 5 pt 5 5 5 pt 5 pt 5 5 5 pt 5 pt 5 5 5 pt 5 pt 5 5 5 pt 5 pt 5 5 5 pt 5 pt 5 set/reset goe1 goe0 toe clk1 clk0 global routing pool (grp) generic logic block (glb) buffers/pins clk3 clk2
specifications isplsi 5384v 5 figure 3. isplsi 5000v generic logic block (glb) glb_5k 01 26667 macrocell 0 pt 160 pt 161 pt 162 pt 163 macrocell 1 macrocell 15 macrocell 31 pt 9 pt 8 pt 7 pt 6 pt 5 pt 0 pt 1 pt 2 pt 3 pt 4 pt 79 pt 78 pt 77 pt 76 pt 75 pt 159 pt 158 pt 157 pt 156 pt 155 to i/o pad to grp ptsa bypass pt clock pt reset pt preset from ptsa ptoe shared pt clock 0 shared pt (p)reset 0 shared pt clock 1 shared pt (p)reset 1 global ptoe 0 ... 5 6 to i/o pad to grp ptsa bypass pt clock pt reset pt preset from ptsa ptoe shared pt clock 0 shared pt (p)reset 0 shared pt clock 1 shared pt (p)reset 1 global ptoe 0 ... 5 6 to i/o pad to grp ptsa bypass pt clock pt reset pt preset from ptsa ptoe shared pt clock 0 shared pt (p)reset 0 shared pt clock 1 shared pt (p)reset 1 global ptoe 0 ... 5 6 to i/o pad to grp ptsa bypass pt clock pt reset pt preset from ptsa ptoe shared pt clock 0 shared pt (p)reset 0 shared pt clock 1 shared pt (p)reset 1 global ptoe 0 ... 5 6 from global routing pool ptsa programmable and array global ptoe bus pt 164
specifications isplsi 5384v 6 figure 4. isplsi 5000v macrocell global ptoe 2 global ptoe 3 global ptoe 0 global ptoe 1 global ptoe 4 global ptoe 5 ptsa dq rp ptsa bypass pt clock pt reset clk en r/l ptoe shared pt clock 0 shared pt clock 1 d/t goe0 goe1 dq d d/t clk en clk register/ latch q rp set/reset pt preset shared pt (p)reset 0 shared pt (p)reset 1 programmable speed/power option toe clk0 clk1 clk clk2 clk3 vccio vccio vcc slew rate 2.5v/3.3v output open drain i/o pad to grp delay
specifications isplsi 5384v 7 global clock distribution the isplsi 5000v family has four dedicated clock input pins - clk0 - clk3. clk0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock speed. the clock inversion is available on the remaining clk1 - clk3 signals. by sharing the pins with the i/o pins, clk2 and clk3 can not only be inverted but also is available for logic implementation through grp signal routing. figure 5 shows these different clock distribution options. figure 5. isplsi 5000v global clock structure clk0 clk1 clk 0 clk 1 io/clk 2 io/clk 3 clk2 clk3 to grp to grp set/reset gset/grst
specifications isplsi 5384v 8 figure 6. boundary scan register circuit for i/o pins figure 7. boundary scan register circuit for input-only pins normal function oe extest update dr scanout (to next cell) clock dr scanin (from previous cell) shift dr normal function toe dq dq dq dq dq i/o pin reset bscan registers bscan latches highz 0 prog_mode extest 1 0 1 scanout (to next cell) clock dr scanin (from previous cell) shift dr dq input pin
specifications isplsi 5384v 9 figure 8. boundary scan waveforms and timing specifications tms tdi tck tdo data to be captured data to be driven out valid data valid data valid data valid data data captured btsu t bth t btcl t btch t btcp t btvo t btco t btoz t btcpsu t btcph t btuov t btuco t btuoz t symbol p arameter min max units t btcp tck [bscan test] clock pulse width 125 ns t btch tck [bscan test] pulse width high 62.5 ns t btcl tck [bscan test] pulse width low 62.5 ns t btsu tck [bscan test] setup time 20 ns t bth tck [bscan test] hold time 25 ns t rf tck [bscan test] rise and fall time 50 mv/ns t btco tap controller falling edge of clock to valid output ?5ns t btoz tap controller falling edge of clock to data output disable ?5ns t btvo tap controller falling edge of clock to data output enable ?5ns t btcpsu bscan test capture register setup time 20 ns t btcph bscan test capture register hold time 25 ns t btuco bscan test update reg, falling edge of clock to valid output ?0ns t btuoz bscan test update reg, falling edge of clock to output disable ?0ns t btuov bscan test update reg, falling edge of clock to output enable ?0ns
specifications isplsi 5384v 10 absolute maximum ratings 1, 2 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v tri-stated output voltage applied ........... -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). 2. compliance with the thermal management section of the lattice semiconductor data book or cd-rom is a requirement. dc recommended operating condition table 2 - 0005/5384 symbol v cc v ccio parameter supply voltage i/o reference voltage commercial t a = 0 c to +70 c min. max. units 3.00 2.3 3.60 3.60 v industrial t a = -40 c to +85 c 3.00 3.60 v v capacitance (t a =25 c,f=1.0 mhz) symbol table 2 - 0006/5384 c parameter clock capacitance 10 units typical test conditions 2 pf v = 3.3v, v = 2.0v cc ck c i/o capacitance 10 1 pf v = 3.3v, v = 2.0v cc i/o c global input capacitance 10 3 pf v = 3.3v, v = 2.0v cc g erase reprogram specification table 2-0008/3320 parameter minimum maximum units isplsi erase/reprogram cycles 10000 cycles
specifications isplsi 5384v 11 switching test conditions input pulse levels table 2 - 0003/5384 input rise and fall time input timing reference levels ouput timing reference levels output load gnd to v ccio min 1.5ns 10% to 90% 1.5v 1.5v see figure 3-state levels are measured 0.5v from steady-state active level. output load conditions (see figure 8) test condition r1 3.3v 2.5v r2 cl a 35pf d 35pf b 35pf 35pf active high slow slew active low c 5pf 5pf 511 511 511 475 475 475 r1 r2 316 316 316 348 348 348 active low to z at v +0.5v ol active high to z at v -0.5v oh table 2 - 0004a/5384 v ol symbol 1. typical values are at v cc = 3.3v and t a = 25 c. table 2 - 0007/5384 v oh v ih v il parameter output low voltage output high voltage input high voltage input low voltage i ol = 8 ma i oh = -4 ma v oh v out or v out v ol (max) v oh v out or v out v ol (max) condition min. typ. max. units 1 2.4 2.0 -0.3 0.4 5.25 0.8 v v v ccio i/o reference voltage 3.0 3.6 v v v dc electrical characteristics for 3.3v range over recommended operating conditions figure 9. test load v ccio r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213d
specifications isplsi 5384v 12 dc electrical characteristics over recommended operating conditions symbol 1. typical values are at v cc = 3.3v and t a = 25 c. 2. pullup is capable of pulling to a minimum voltage of v oh under no-load conditions. dc char_5000v i pu i bhl parameter i bhh i bhlo 2 i/o active pullup current bus hold low sustaining current bus hold high sustaining current bus hold low overdrive current i ih i il input or i/o high leakage current input or i/o low leakage current 0v v v (max.) in il condition min. typ. max. units 1 40 -40 -10 10 -150 50 550 a a a a a a i bhlh i bht bus hold high overdrive current bus hold trip points v il -550 v ih a v i vccio current needed for v ccio pin all i/os pulled-up, (total i/os * i pumax ) 45 ma a (v ccio -0.2)v v in v ccio v ccio v in 5.25v 0v v in v il 0v v in v ccio 0v v in v ccio v in v il(max) v in v ih(min) dc electrical characteristics for 2.5v range over recommended operating conditions v ih symbol 2.5v/5000 v oh parameter input high voltage output high voltage v oh(min) v out or v out v ol(max) v oh(min) v out or v out v ol(max) v ccio=min , v in =v ih or v il , i oh = -2ma v ccio=min , v in =v ih or v il , i ol = 2ma condition min. typ. max. units 1.7 1.7 5.25 v v ccio v il i/o reference voltage input low voltage 2.3 -0.3 2.7 0.7 v v v v ccio=min , v in =v ih or v il , i oh = -100 a 2.1 v 0.7 v v ccio=min , v in =v ih or v il , i ol = 100 a 0.2 v v ol output low voltage
specifications isplsi 5384v 13 external switching characteristics over recommended operating conditions . m a r a p t s e t 3 . d n o c #n o i t p i r c s e d 5 , 4 5 2 1 -0 0 1 -0 7 - s t i n u . n i m. x a m. n i m. x a m. n i m. x a m t 1 d p a1 s s a p y b t p 5 , y a l e d . p o r p a t a d5 . 70 1 5 1s n t 2 d p a2 y a l e d n o i t a g a p o r p a t a d5 . 93 1 9 1s n f x a m a3 k c a b d e e f l a n r e t n i h t i w y c n e u q e r f k c o l c 1 5 2 1 0 0 10 7 z h m f ) . t x e ( x a m ? ) 1 o c t + 2 u s t ( / 1 , k c a b d e e f . t x e h t i w . q e r f k c o l c7 8 5 . 4 65 . 3 4 z h m f ) . g o t ( x a m ? e l g g o t x a m , y c n e u q e r f k c o l c 2 7 6 1 5 2 13 8 z h m t 1 u s ? s s a p y b t p 5 , k l c e r o f e b e m i t p u t e s . g e r b l g682 1 s n t 1 o c a7 y a l e d t u p t u o o t k c o l c . g e r b l g45 . 58 s n t 1 h ? s s a p y b t p 5 , k c o l c r e t f a e m i t d l o h . g e r b l g 0?? s n t 2 u s ? k c o l c e r o f e b e m i t p u t e s . g e r b l g5 . 70 1 5 1 s n t 2 h ? 1k c o l c r e t f a e m i t d l o h . g e r b l g 0?? s n t 3 u s ? 1 . g e r t u p n i , k c o l c e r o f e b e m i t p u t e s . g e r b l g h t a p 68 2 1 s n t 3 h ? 1h t a p . g e r t u p n i , k c o l c r e t f a e m i t d l o h . g e r b l g 0?? s n t 1 r a3 1y a l e d t u p t u o o t n i p t e s e r . t x e5 1 0 20 3s n t 1 w r ? 1n o i t a r u d e s l u p t e s e r . t x e794 1 s n t s i d / e o t p c / b5 1e l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a c o l92 1 8 1s n t s i d / e o t p g c / b6 1e l b a s i d / e l b a n e t u p t u o m r e t t c u d o r p l a b o l g8 1 4 20 3s n t s i d / e o g c / b7 1e l b a s i d / e l b a n e t u p t u o o t t u p n i e o l a b o l g 68 2 1s n t h w ? 1h g i h , n o i t a r u d e s l u p k c o l c . c n y s . t x e346s n t l w ? 1w o l , n o i t a r u d e s l u p k c o l c . c n y s . t x e346s n . k c a b d e e f p r g g n i s u r e t n u o c t i b - 2 3 d r a d n a t s . 1 . % 0 5 n a h t r e h t o f o e l c y c y t u d k c o l c a r o f w o l l a o t s i s i h t . ) l w t + h w t ( / 1 n a h t s s e l e b y a m ) e l g g o t ( x a m f . 2 . n o i t c e s s n o i t i d n o c t s e t g n i h c t i w s e c n e r e f e r . 3 . 0 k l c d n a , b l g 1 f o d a o l p r g a , t u o n a f a s t p e s a c t s r o w h t i w n e k a t e r a s r e b m u n g n i m i t l l a , e s i w r e h t o d e t o n s s e l n u . 4 . r e v i r d t u p t u o e v i t c a l a m r o n g n i s u d e r u s a e m s r e t e m a r a p g n i m i t . 5 s p e . 4 8 3 5 . t x e g n i m i t
specifications isplsi 5384v 14 internal timing parameters 1 over recommended operating conditions i/o buffer t idcom 22 input pad and buffer, combinatorial input 0.7 0.9 1.4 ns t idreg 23 input pad and buffer, registered input 4.7 6.6 9.7 ns t odcom 24 output pad and buffer, combinatorial output 1.3 2 2.6 ns t odreg 25 output pad and buffer, registered output 1.8 2.8 4.6 ns t odz 26 output buffer enable/disable 1.3 1.7 2.6 ns t slf 27 slew rate adder, fast slew ??? ns t sls 28 slew rate adder, slow slew 7.5 10 15 ns t slfd 29 programmable delay adder, fast slew 0.5 0.7 1 ns t slsd 30 programmable delay adder, slow slew 8 10.7 16 ns glb/macrocell delay register t mbp 31 macrocell register/latch bypass ??? ns t mlat 32 macrocell latch delay 1 1.4 2 ns t mco 33 macrocell register/latch clock to output ??? ns t msu 34 macrocell register/latch setup time 1 1.1 1.7 ns t mh 35 macrocell register/latch hold time 2.5 3.9 5.3 ns t msuce 36 macrocell register/latch clken setup time 1 1.4 2 ns t mhce 37 macrocell register/latch clken hold time 1 1.4 2 ns t mrst 38 macrocell register/latch set/reset time 1 1.4 2 ns t ftog 39 toggle flip-flop feedback 1 1.3 2 ns and array t andhs 40 and array, high speed mode ??? ns t andlp 41 and array, low power mode 5 6.6 10 ns ptsa t 5ptcom 42 5 product term bypass, combinatorial 1 1.4 2 ns t 5ptreg 43 5 product term bypass, registered 1 1.7 2.3 ns t 5ptxcom 44 5 product term xor, combinatorial 2.5 3.6 5 ns t 5pxtreg 45 5 product term xor, registered 1.5 2.2 3.3 ns t ptsacom 46 product term sharing array, combinatorial 3 4.1 6 ns t ptsareg 47 product term sharing array, registered 2.0 2.7 4.3 ns ptsa controls t pck 48 product term clock delay 0.5 0.7 1 ns t pcken 49 product term clken delay 1 1.4 2 ns t scken 50 shared product term clken delay 1 1.4 2 ns t sck 51 shared product term clock delay 0.5 0.7 1 ns t ptsacken 52 product term sharing array clken delay 2.0 2.4 4 ns t srst 53 shared product term set/reset delay 2.5 3.4 5 ns t prst 54 product term set/reset delay 1.5 ?? ns t poe 55 product term output enable/disable 2.5 3.4 5 ns t gpoe 56 global pt output enable/disable 11.5 15.4 17 ns -125 -100 -70 min max min max min max unit param # description 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details.
specifications isplsi 5384v 15 isplsi 5384v timing model pt controls register dedicated input buffers output buffer i/o pad i/o pad input output ptsa grp t grpi glb/macrocell t andhs t goe t gclk0 t grst t toe t slfd t andlp t 5ptcom t 5ptreg t 5ptxreg t 5ptxcom t ptsacom t ptsareg t sck t pck t ptsacken t srst t poe t gpoe t idcom t mh t msuce t mrst t mhce t mco t grpm tpcken tscken t slsd slew input pad t prst t idreg buffer delays and array t gclken1 t gclken0 t gclk123 t ftog t slf t sls input buffer #20 #21 #56 #38 #39 #40 #44 #42 #41 #45 #43 #49 #46 t mbp #29 t odcom #22 #28 #27 #25 #26 t odreg #23 t odz #24 #37 t mlat #30 t msu #32 #33 #31 #35 #34 #36 #50 #47 #48 #51 #52 #53 #54 #57 #58 #59 #60 #61 #62 #63 #55 internal timing parameters 1 over recommended operating conditions grp t grpi 57 grp delay from i/o pad 1.5 ?? ns t grpm 58 grp delay from macrocell 1.0 1.2 1.2 ns global control delays t gclk01 59 global clock 0 or 1 delay 1.2 1.7 2.4 ns t gclk23 60 global clock 2 or 3 delay 2.2 2.7 4.4 ns t gclken0 61 global clken 0 delay 1.7 2.4 3.4 ns t gclken1 62 global clken 1 delay 2.7 3.4 5.4 ns t grst 63 global set/reset delay 12.2 15.8 23.4 ns t goe 64 global oe delay 4.7 6.3 9.4 ns t toe 65 test oe delay 4.7 6.2 9.4 ns -125 -100 -70 min max min max min max unit param # description 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details.
specifications isplsi 5384v 16 power consumption complete group of four. the fast "high-speed" setting operates product terms at their normal full power con- sumption. for portions of the logic that can tolerate longer propagation delays, selecting the slower "low- power" setting will significantly reduce the power dissipation for these product terms. figure 10 shows the relationship between power and operating speed. power consumption in the isplsi 5384v device depends on two primary factors: the speed at which the device is operating and the number of product terms used. the product terms have a fuse-selectable speed/power tradeoff setting. each group of four product terms has a single speed/power tradeoff control fuse that acts on the 200 0 20 40 60 80 100 120 140 f max (mhz) i cc (ma) notes: configuration of 24 16-bit counters typical current at 3.3v, 25 c isplsi 5384va high speed mode isplsi 5384va low power mode 0127/5384 i cc can be estimated for the isplsi 5384va using the following equation: high speed mode: icc = 40 + (# of pts * 0.432) + (# of nets * max. freq * 0.0045) low power mode: icc = 40 + (# of pts * 0.161) + (# of nets * max. freq * 0.0045) # of pts = number of product terms used in design # of nets = number of signals used in device max. freq = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of 2 glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 300 400 500 550 450 350 250 600 150 figure 10. typical device power consumption vs fmax
specifications isplsi 5384v 17 tms input - this pin is the test mode select input, which is used to control the jtag state machine. tck input - this pin is the test clock input pin used to clock through the jtag state machine. tdi input - this pin is the jtag test data in pin used to load data. tdo output - this pin is the jtag test data out pin used to shift data out. toe / i/o0 input/output - this pin functions as either the test output enable pin or an i/o pin based upon customer's design. toe tristates all i/o pins when a logic low is driven. goe0, goe1 input - these two pins are the global output enable input pins. gset/grst dedicated set/reset input - this pin is available to all registers in the device and can independently be configured as preset, reset or no effect on each register. the global polarity (active high or low input) for this pin is also selectable. i/o input/output ?these are the general purpose i/o used by the logic array. gnd ground nc 1 no connect. vcc vcc clk0, clk1 dedicated clock inputs for all registers. both clocks are muxed before being used as the clock input to all registers in the device. clk2 / i/o, input/output - these pins function as either dedicated clock inputs for all registers or an i/o clk3 / i/o pin based upon customer's design. both clocks are muxed before being used as the clock input to all registers in the device. vccio input - this pin is used if an optional 2.5v output is to be used. every io can independently select either 3.3v or the optional voltage as its output level. if the optional output voltage is not required, this pin must be connected to the vcc supply. programmable pull-up resistors and bus-hold latches only draw current from this supply. signal descriptions signal name description 1. nc pins are not to be connected to any active signals, vcc or gnd.
specifications isplsi 5384v 18 goe0, goe1 78, 79 toe / i/o0 32 gset/grst 138 tck 29 tdi 30 tdo 136 tms 28 clk0, clk1 184,185 clk2 / i/o89 162 clk3 / i/o98 173 vccio 137 gnd 3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199 vcc 7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201 nc 49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208 signal locations (208-pin pqfp) signal pin 1. ncs are not to be connected to any active signals, vcc or gnd.
specifications isplsi 5384v 19 i/o locations (208-pin pqfp) i/o # pin i/o # pin i/o # pin i/o # pin i/o # pin i/o # pin * i/o 89 is multiplexed with clk2, i/o 98 is multiplexed with clk3 and i/o 0 is multiplexed with toe. 0* 32 133 234 335 436 537 638 740 842 943 10 44 11 45 12 46 13 47 14 53 15 54 16 55 17 56 18 57 19 59 20 60 21 62 22 63 23 64 24 65 25 66 26 67 27 68 28 70 29 71 30 72 31 73 32 74 33 75 34 76 35 81 36 82 37 83 38 84 39 85 40 86 41 87 42 89 43 91 44 92 45 93 46 94 47 95 48 96 49 97 50 98 51 100 52 111 53 112 54 114 55 115 56 116 57 117 58 118 59 119 60 120 61 122 62 124 63 125 64 126 65 127 66 129 67 130 68 131 69 132 70 133 71 134 72 140 73 141 74 142 75 143 76 144 77 145 78 146 79 147 80 148 81 149 82 151 83 153 84 154 85 155 86 159 87 160 88 161 89* 162 90 163 91 165 92 166 93 167 94 168 95 169 96 171 97 172 98* 173 99 174 100 175 101 176 102 178 103 180 104 181 105 182 106 183 107 187 108 188 109 189 110 190 111 192 112 193 113 194 114 195 115 196 116 197 117 198 118 200 119 202 120 203 121 204 122 205 123 206 124 1 125 2 126 4 127 5 128 6 129 8 130 9 131 10 132 11 133 13 134 15 135 16 136 17 137 18 138 20 139 21 140 23 141 24 142 25 143 26
specifications isplsi 5384v 20 goe0, goe1 p9, p10 toe / i/o0 k1 gset/grst h14 tck k2 tdi k3 tdo g14 tms j1 clk0, clk1 a7, b8 clk2 / i/o89 b13 clk3 / i/o98 a11 vccio h15 gnd d10, d12, d13, d5, d7, d8, e4, f13, g4, g8, g9, h10, h13, h7, j10, j13, j4, j7, k8, k9, l13, l4, m13, n10, n12, n4, n5, n7, n8 vcc d11, d4, d6, d9, e13, f4, g10, g13, g7, h4, h8, h9, j8, j9, k10, k13, k4, k7, m4, n11, n13, n6, n9 nc 1 e15, c14 signal locations (208-ball bga) signal ball 1. ncs are not to be connected to any active signals, vcc or gnd.
specifications isplsi 5384v 21 i/o locations (208-ball bga) i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball * i/o 89 is multiplexed with clk2, i/o 98 is multiplexed with clk3 and i/o 0 is multiplexed with toe. 0* k1 1l2 2l1 3l3 4m1 5m2 6m3 7n1 8n3 9n2 10 p2 11 p1 12 r1 13 r2 14 r3 15 p3 16 t1 17 p4 18 r4 19 r5 20 p5 21 t2 22 r6 23 t3 24 t4 25 t5 26 r7 27 p6 28 t6 29 t7 30 r8 31 p8 32 p7 33 t8 34 t9 35 r9 36 r10 37 t10 38 t11 39 t12 40 t13 41 t14 42 p11 43 p12 44 r11 45 t15 46 t16 47 r14 48 r12 49 p14 50 p13 51 r13 52 r15 53 p15 54 r16 55 p16 56 n15 57 n14 58 m14 59 n16 60 m15 61 m16 62 l14 63 l15 64 l16 65 k14 66 k15 67 k16 68 j14 69 j15 70 j16 71 h16 72 g16 73 f14 74 g15 75 f16 76 e14 77 f15 78 e16 79 d16 80 c16 81 b16 82 d15 83 d14 84 a16 85 c15 86 b15 87 a15 88 b14 89* b13 90 c13 91 a14 92 c12 93 b12 94 a13 95 a12 96 c11 97 b11 98* a11 99 b10 100 a10 101 c10 102 b9 103 c9 104 a9 105 a8 106 c8 107 c7 108 b7 109 a6 110 a5 111 c6 112 b6 113 a4 114 a3 115 a2 116 c5 117 b5 118 b4 119 c4 120 c3 121 c2 122 b3 123 b2 124 a1 125 d2 126 b1 127 d3 128 e2 129 c1 130 e3 131 d1 132 f2 133 e1 134 f1 135 g2 136 f3 137 h2 138 h3 139 g3 140 g1 141 h1 142 j2 143 j3
specifications isplsi 5384v 22 goe0, goe1 v11, u11 toe / i/o 0 m2 gset/grst j18 tck l4 tdi m1 tdo j20 tms l3 clk0, clk1 c10, d10 clk2 / i/o 119 a18 clk3 / i/o 131 b13 vccio j19 gnd a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, n4, n17, u4, u8, u13, u17 vcc d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 nc 1 u1, w1, e2, u2, w2, y2, b3, c3, d3, u3, c5, w4, t4, y12, a17, t17, w17, b18, c18, b19, c19, d19, w19, b20, t20, w20, y20, p19, r3 signal locations (272-ball grid array) signal ball 1. ncs are not to be connected to any active signals, vcc or gnd.
specifications isplsi 5384v 23 i/o locations (272-ball grid array) * i/o 119 is multiplexed with clk2, i/o 131 is multiplexed with clk3 and i/o 0 is multiplexed with toe. 0* m2 1m3 2m4 3n1 4n2 5n3 6p1 7p2 8r1 9p3 10 r2 11 t1 12 p4 13 t2 14 t3 15 v1 16 v2 17 v3 18 y1 19 w3 20 v4 21 u5 22 y3 23 y4 24 v5 25 w5 26 y5 27 v6 28 u7 29 w6 30 y6 31 v7 32 w7 33 y7 34 v8 35 w8 36 y8 37 u9 38 v9 39 w9 40 y9 41 w10 42 v10 43 y10 44 y11 45 w11 46 w12 47 v12 48 u12 49 y13 50 w13 51 v13 52 y14 53 w14 54 y15 55 v14 56 w15 57 y16 58 u14 59 v15 60 w16 61 y17 62 v16 63 y18 64 u16 65 v17 66 w18 67 y19 68 v18 69 v19 70 u19 71 u18 72 v20 73 u20 74 t18 75 t19 76 r18 77 p17 78 r19 79 r20 80 p18 81 p20 82 n18 83 n19 84 n20 85 m17 86 m18 87 m19 88 m20 89 l19 90 l18 91 l20 92 k20 93 k19 94 k18 95 k17 96 j17 97 h20 98 h19 99 h18 100 g20 101 g19 102 f20 103 g18 104 f19 105 e20 106 g17 107 f18 108 e19 109 d20 110 e18 111 c20 112 e17 113 d18 114 a20 115 a19 116 b17 117 c17 118 d16 119* a18 120 c16 121 b16 122 a16 123 c15 124 d14 125 b15 126 a15 127 c14 i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball 128 b14 129 a14 130 c13 131* b13 132 a13 133 d12 134 c12 135 b12 136 a12 137 b11 138 c11 139 a11 140 a10 141 b10 142 a9 143 b9 144 c9 145 d9 146 a8 147 b8 148 c8 149 a7 150 b7 151 a6 152 c7 153 b6 154 a5 155 d7 156 c6 157 b5 158 a4 159 b4 160 a3 161 d5 162 c4 163 b2 164 a2 165 b1 166 c2 167 d2 168 e4 169 c1 170 d1 171 e3 172 e1 173 f3 174 g4 175 f2 176 f1 177 g3 178 g2 179 g1 180 h3 181 h2 182 h1 183 j4 184 j3 185 j2 186 j1 187 k2 188 k3 189 k1 190 l1 191 l2
specifications isplsi 5384v 24 goe0, goe1 af14, ad13 toe / i/o0 t1 gset/grst l25 tck t2 tdi r3 tdo n24 tms r1 clk0, clk1 a13, c14 clk2 / i/o179 a23 clk3 / i/o197 b17 vccio m26 gnd a1, a2, a26, b2, b25, b26, c3, c24, d4, d9, d14, d19, d23, h4, j23, l11, l12, l13, l14, l15, l16, m11, m12, m13, m14, m15, m16, n4, n11, n12, n13, n14, n15, n16, p11, p12, p13, p14, p15, p16, p23, r11, r12, r13, r14, r15, r16, t11, t12, t13, t14, t15, t16, v4, w23, ac4, ac8, ac13, ac18, ac23, ad3, ad24, ae1, ae2, ae25, af1, af25, af26 vcc d6, d11, d16, d21, f4, f23, l4, l23, t4, t23, aa4, aa23, ac6, ac11, ac16, ac21 nc 1 c9, d2, e24, l1, ac25, af19 signal locations (388-ball grid array) signal ball 1. ncs are not to be connected to any active signals, vcc or gnd.
specifications isplsi 5384v 25 i/o locations (388-ball grid array) 0* t1 1r4 2u2 3t3 4u1 5u4 6v2 7u3 8v1 9w2 10 w1 11 v3 12 y2 13 w4 14 y1 15 w3 16 aa2 17 y4 18 aa1 19 y3 20 ab2 21 ab1 22 aa3 23 ac2 24 ab4 25 ac1 26 ab3 27 ad2 28 ac3 29 ad1 30 af2 31 ae3 32 af3 33 ae4 34 ad4 35 af4 36 ae5 37 ac5 38 ad5 39 af5 40 ae6 41 ac7 42 ad6 43 af6 44 ae7 45 af7 46 ad7 47 ae8 48 ac9 49 af8 50 ad8 51 ae9 52 af9 53 ae10 54 ad9 55 af10 56 ac10 57 ae11 58 ad10 59 af11 60 ae12 61 af12 62 ad11 63 ae13 64 ac12 65 af13 66 ad12 67 ae14 68 ac14 69 ae15 70 ad14 71 af15 72 ae16 73 ad15 74 af16 75 ac15 76 ae17 77 ad16 78 af17 79 ac17 80 ae18 81 ad17 82 af18 83 ae19 84 ad18 85 ae20 86 ac19 87 af20 88 ad19 89 ae21 90 ac20 91 af21 92 ad20 93 ae22 94 af22 95 ad21 96 ae23 97 ac22 98 af23 99 ad22 100 ae24 101 ad23 102 af24 103 ae26 104 ad25 105 ad26 106 ac24 107 ac26 108 ab25 109 ab23 110 ab24 111 ab26 112 aa25 113 y23 114 aa24 115 aa26 116 y25 117 y26 118 y24 119 w25 120 v23 121 w26 122 w24 123 v25 124 v26 125 u25 126 v24 127 u26 128 u23 129 t25 130 u24 131 t26 132 r25 133 r26 134 t24 135 p25 136 r23 137 p26 138 r24 139 n25 140 n23 141 n26 142 p24 143 m25 144 m24 145 l26 146 m23 147 k25 148 l24 149 k26 150 k23 151 j25 152 k24 153 j26 154 h25 155 h26 156 j24 157 g25 158 h23 159 g26 160 h24 161 f25 162 g23 163 f26 164 g24 165 e25 166 e26 167 f24 168 d25 169 e23 170 d26 171 c25 172 d24 173 c26 174 a25 175 b24 176 a24 177 b23 178 c23 179* a23 180 b22 181 d22 182 c22 183 a22 184 b21 185 d20 186 c21 187 a21 188 b20 189 a20 190 c20 191 b19 192 d18 193 a19 194 c19 195 b18 196 a18 197* b17 198 c18 199 a17 200 d17 201 b16 202 c17 203 a16 204 b15 205 a15 206 c16 207 b14 208 d15 209 a14 210 c15 211 b13 212 d13 213 b12 214 c13 215 a12 216 b11 217 c12 218 a11 219 d12 220 b10 221 c11 222 a10 223 d10 224 b9 225 c10 226 a9 227 b8 228 a8 229 b7 230 d8 231 a7 232 c8 233 b6 234 d7 235 a6 236 c7 237 b5 238 a5 239 c6 240 b4 241 d5 242 a4 243 c5 244 b3 245 c4 246 a3 247 b1 248 c2 249 c1 250 d3 251 d1 252 e2 253 e4 254 e3 255 e1 256 f2 257 g4 258 f3 259 f1 260 g2 261 g1 262 g3 263 h2 264 j4 265 h1 266 h3 267 j2 268 j1 269 k2 270 j3 271 k1 272 k4 273 l2 274 k3 275 m2 276 m1 277 l3 278 n2 279 m4 280 n1 281 m3 282 p2 283 p4 284 p1 285 n3 286 r2 287 p3 i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball i/o # ball * i/o 179 is multiplexed with clk2, i/o 197 is multiplexed with clk3 and i/o 0 is multiplexed with toe.
specifications isplsi 5384v 26 isplsi 5384v top view 208-pqfp/5384v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 1. nc pins are not to be connected to any active signal, vcc or gnd. 2. pins have dual function capability. i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 gnd i/o 19 i/o 20 vcc i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 gnd i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 gnd goe0 goe1 vcc i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 gnd i/o 42 vcc i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 gnd i/o 51 1 nc 1 nc 1 nc 1 nc nc 1 nc 1 i/o 123 i/o 122 i/o 121 i/o 120 i/o 119 vcc i/o 118 gnd i/o 117 i/o 116 i/o 115 i/o 114 i/o 113 i/o 112 i/o 111 gnd i/o 110 i/o 109 i/o 108 i/o 107 vcc clk1 clk0 i/o 106 i/o 105 i/o 104 i/o 103 gnd i/o 102 vcc i/o 101 i/o 100 i/o 99 i/o 98 / clk3 2 i/o 97 i/o 96 gnd i/o 95 i/o 94 i/o 93 i/o 92 i/o 91 gnd i/o 90 i/o 89 / clk2 2 i/o 88 i/o 87 i/o 86 nc 1 nc 1 vcc i/o 85 i/o 84 i/o 83 vcc i/o 82 gnd i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 vcc gset/grst vccio tdo gnd i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 gnd i/o 65 i/o 64 i/o 63 i/o 62 vcc i/o 61 gnd i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 gnd i/o 53 i/o 52 vcc nc 1 nc 1 nc 1 nc 1 nc 1 i/o 124 i/o 125 gnd i/o 126 i/o 127 i/o 128 vcc i/o 129 i/o 130 i/o 131 i/o 132 gnd i/o 133 vcc i/o 134 i/o 135 i/o 136 i/o 137 gnd i/o 138 i/o 139 vcc i/o 140 i/o 141 i/o 142 i/o 143 gnd tms tck tdi vcc 2 i/o 0 / toe i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 gnd i/o 7 vcc i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 gnd 1 nc 1 nc 1 nc 1 nc pin configuration isplsi 5384v 208-pin pqfp (with heat spreader)
specifications isplsi 5384v 27 part number description ordering information commercial device number grade blank = commercial isplsi 5384v xxx x xxxx speed 125 = 125 mhz f max 100 = 100 mhz f max 70 = 70 mhz f max power l = low package q208 = 208-pqfp (with heat spreader) b208 = 208-bga b272 = 272-bga b388 = 388-bga device family x 0212/5384 y l i m a ff x a m t d p r e b m u n g n i r e d r oe g a k c a p i s l p s i 5 2 15 . 78 0 2 q l 5 2 1 - v 4 8 3 5 i s l p s ip f q p n i p - 8 0 2 i s l p s i 5 2 15 . 78 0 2 b l 5 2 1 - v 4 8 3 5 i s l p s ia g b l l a b - 8 0 2 i s l p s i 5 2 15 . 72 7 2 b l 5 2 1 - v 4 8 3 5 i s l p s ia g b l l a b - 2 7 2 i s l p s i 5 2 15 . 78 8 3 b l 5 2 1 - v 4 8 3 5 i s l p s ia g b l l a b - 8 8 3 i s l p s i 0 0 10 18 0 2 q l 0 0 1 - v 4 8 3 5 i s l p s ip f q p n i p - 8 0 2 i s l p s i 0 0 10 18 0 2 b l 0 0 1 - v 4 8 3 5 i s l p s ia g b l l a b - 8 0 2 i s l p s i 0 0 10 12 7 2 b l 0 0 1 - v 4 8 3 5 i s l p s ia g b l l a b - 2 7 2 i s l p s i 0 0 10 18 8 3 b l 0 0 1 - v 4 8 3 5 i s l p s ia g b l l a b - 8 8 3 i s l p s i 0 75 18 0 2 q l 0 7 - v 4 8 3 5 i s l p s ip f q p n i p - 8 0 2 i s l p s i 0 75 18 0 2 b l 0 7 - v 4 8 3 5 i s l p s ia g b l l a b - 8 0 2 i s l p s i 0 75 12 7 2 b l 0 7 - v 4 8 3 5 i s l p s ia g b l l a b - 2 7 2 i s l p s i 0 75 18 8 3 b l 0 7 - v 4 8 3 5 i s l p s ia g b l l a b - 8 8 3

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